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Multi-core processor
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#	Item
581	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
582	Call for Workshops and Tutorials 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP[removed]The ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP[removed]is see Add to Reading List Source URL: research.ihost.com Language: English - Date: 2007-03-15 09:44:07 Programming language theory Parallel computing SIGPLAN ALGOL 68 Multi-core processor Computing Symposium on Principles and Practice of Parallel Programming Computer science
583	Theme Feature . A Single-Chip Multiprocessor Add to Reading List Source URL: www-hydra.stanford.edu Language: English - Date: 1998-03-07 07:33:31 Parallel computing Central processing unit Microprocessors Threads Simultaneous multithreading Superscalar Multithreading Microarchitecture Multi-core processor Computing Computer architecture Computer hardware
584	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
585	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.edu Add to Reading List Source URL: www-hydra.stanford.edu Language: English* - Date: 1999-11-05 21:09:40 Computer architecture CPU cache Cache Central processing unit Multi-core processor Parallel computing Direct memory access Harvard architecture Computer hardware Computing Computer memory
586	Low-Pain, High-Gain Multicore Programming in Haskell Coordinating Irregular Symbolic Computations on MultiCore Architectures A. Al Zain P. Trinder M. Aswad G. Michaelson Add to Reading List Source URL: www.macs.hw.ac.uk Language: English - Date: 2009-02-04 11:56:44 Parallel computing Algorithmic skeleton Multi-core processor Haskell Thread OpenMP Parallel programming model Task parallelism Actor model Computing Concurrent computing Computer programming
587	Extreme Scale Computer Architecture: Energy Efficiency from the Ground Up Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-06-21 19:03:22 Voltage regulator Multi-core processor Electronics Electronic engineering Electromagnetism
588	Characterizing the Impact of End-System Affinities On the End-to-End Performance of High-Speed Flows Nathan Hanford1 , Vishal Ahuja1 , Mehmet Balman2 , Matthew K. Farrens1 , Dipak Ghosal1 , Eric Pouyoul2 and Brian Tierne Add to Reading List Source URL: www.es.net Language: English - Date: 2014-12-11 12:32:11 Computer memory Scheduling algorithms Microprocessors Computer architecture Multi-core processor Parallel computing AMD 10h Jumbo frame CPU cache Computing Computer hardware Concurrent computing
589	Journal of Instruction-Level Parallelism Vol. 3 Submitted[removed]; Published 2002 The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2002-04-12 01:25:15 Theoretical computer science Computing Parallel computing Heat transfer Mathematical optimization Multi-core processor Mathematics Applied mathematics Operations research Algorithm Mathematical logic
590	Microsoft Word - nwpsaf-mo-vs-043_as10_01_report.doc Add to Reading List Source URL: nwpsaf.eu Language: English - Date: 2012-02-22 13:39:52 Graphics hardware Video cards GPGPU CUDA Nvidia Tesla Advanced Microwave Sounding Unit GPU cluster Graphics processing unit Multi-core processor Computer hardware Computing Nvidia

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